One catch:
P.S. To fully unlock the access, must write 0xACCE00FF (0xACCE is to prevent random accidental write, otherwise is silently ignored)ACCESSCTRL: CORESIGHT_TRACE Register
Offset: 0x58
Description: Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so.
Bit 6 DMA: If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. RW Default at reset: 0x0
Statistics: Posted by gmx — Fri Nov 08, 2024 12:23 am