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Bare metal, Assembly language • Re: rpi4 os: context switch breaks irq

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Hey,
I dont really understand what you mean by the first question, but right before the context switch I call:

Code:

enable_irq:    msr    daifclr, #2    ret
which should do what you mean I think?

The timer is rearmed with a new delay befor the context switch:

Code:

        #define MMIO_BASE       0xFE000000    #define PIT_Compare3    (MMIO_BASE+0x00003018)    #define PIT_LOW         (MMIO_BASE+0x00003004)    #define PIT_STATUS      (MMIO_BASE+0x00003000)    #define PIT_MASKBIT     3        void timer_handler(void) {    printf("t ");    mmio_write(PIT_Compare3, mmio_read(PIT_LOW) + timer_frq);    mmio_write(PIT_STATUS, 1 << PIT_MASKBIT);    timer_tick();}
And I think I am properly ack'ing the interrupt:

Code:

#define GICC_BASE       0xFF842000#define GICC_ACK        (GICC_BASE + 0x00c)#define GICC_EOI        (GICC_BASE + 0x010)#define GIC_SPURIOUS    1023#define PIT_SPI         99void dispatch(void) {    printf("ir_");    unsigned int spi = mmio_read(GICC_ACK);    while (spi != GIC_SPURIOUS) { // Loop until no SPIs are pending        if (spi == PIT_SPI) {            mmio_write(GICC_EOI, spi); // Signal the end of the interrupt            timer_handler(); // Call the timer handler            break;        }    }}
Returning from the interrupt handler might be a problem, because after the context switch it return to the next process in line and not to the interrupt handler. That is the reason why I write the end of the interrupt before I call the timer_handler().
Note that I only copied code in the example which I think is relevant.

Statistics: Posted by JonasPfi — Fri Oct 18, 2024 11:20 pm



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